1. Field of the Invention
The present invention relates to a driver unit for driving an active matrix LCD device in a dot reversible driving scheme and, more particularly, to a structure of the horizontal driver in the driver unit.
2. Description of the Related Art
Active matrix LCD devices are now used in a variety of applications due to their advantages of light weight, low operating voltage, low power dissipation and small thickness. FIG. 1 shows a conventional active matrix LCD module including a drive unit 200 in a dot reversible driving scheme.
The LCD panel 100 includes front and rear panels sandwiching therebetween liquid crystal. The rear panel has a plurality of pixel elements arranged in a matrix and each including a TFT (thin film transistor) and a pixel electrode, whereas the front panel has a common electrode and color filters. The rear panel includes a plurality of gate lines arranged in a vertical direction and each extending in a horizontal direction for driving the gates of TFTs arranged in a row, and a plurality of data lines arranged in the horizontal direction and each extending in the vertical direction for supplying display data to the pixels arranged in a column direction.
The drive unit 200 includes a vertical driver 210 fro driving the gate lines and a horizontal driver 220 for driving the data lines. When the vertical driver 210 supplies a scanning signal to a horizontal gate line for turning on the corresponding TFTs in the row, and the horizontal driver supplies a display data to each of the vertical data lines, an analog display signal is supplied to the pixel electrode through a corresponding TFT, whereby an electric field is applied to the liquid crystal between the pixel electrode and the common electrode. The electric field generates a chemical change in the liquid crystal for displaying an image based on the display data.
Assuming that the LCD panel defines 1024 (horizontal)xc3x97768 (vertical) pixels therein, the configurations of the vertical driver 210 and the horizontal driver 220 are such that:
(1) the horizontal driver drives 3072 (3xc3x971024) data lines each assigned for red, green and blue, and includes eight cascaded driving sections each having a function fro driving 384 data lines and arranged at the top of the LCD panel; and
(2) the vertical driver drives 768 gate lines and includes four cascaded driving sections each having a function for driving 192 gate lines and arranged at one side of the Lcd panel.
Each of the vertical and horizontal drivers 210 and 220 is implemented on a single IC chip, which is mounted on a TCP (tape carrier package) and disposed with the longer sides thereof being parallel to a corresponding side of the LCD panel.
The horizontal driver 220, such as shown in FIG. 2, delivers display data to the data lines S1 to S384 including R, G and B color data having a positive or negative polarity with 64 gray-scale levels so that each data line S1 to S348 receives an alternate driving signal, and so that an odd-numbered data line S1, S3, S5, . . . and an even-numbered data line S2, S4, S6, . . . receive driving signals having different polarities in each horizontal period.
The horizontal driver 220 includes a shift register 221, a data register block 222, a latch block 223, a level shifter block 224, a D/A converter block 225 and an output stage block 226 including voltage followers. The shift register 221 is a 64-bit bi-directional register, which responds to a direction selection signal to select a right-shift operation or a left-shift operation for shifting a start pulse. The direction of the shift pulse is determined during the initial adjustment of the device. The shift register 221 reads a high level of a start pulse at a rising edge of a clock signal, generates successive control signals for the data register block 222 by shifting the start pulse, and delivers the control signals for controlling the data register 222 to receive input display data.
A group of six 6-bit data registers in the data register block 222 reads 6-bit display data at a time based on the control signals of the shift register 221. Each latch in the data latch block 223 responds to a rising edge of a latch control signal to latch the display data from the data register block 222, whereby the data latch block 222 delivers the display data for one row in a horizontal period through the level shifter block 224 to the D/A converter block 225. The D/A converter block 225 generates 64-level gray-scale voltages having a positive polarity and 64-level gray-scale voltages having a negative polarity in a gray-scale voltage generator of D/A converter block 225, consecutively selects one of the gray-scale voltages based on a display data by using a ROM decoder thereof, and delivers a gray-scale signal having a selected one of the gray-scale voltages through the voltage follower 226 as a driving voltage for driving each data line. The driving voltages for the data lines are such that each odd-numbered data line S1, S3, S5, . . . and each even-numbered data line S2, S4, S6, . . . are driven by the driving voltages having different polarities in each horizontal period, and each data line S1 to S348 receives alternately a positive-polarity signal and a negative-polarity signal in each horizontal period.
Referring to FIG. 3, a semiconductor chip 301 implementing the horizontal driver 220 of FIG. 2 and mounted on a TCP is exemplified. The horizontal driver 220 has a function for driving 384 data lines, for example. The semiconductor chip 301 has a rectangular shape in the top plan view thereof, and includes the horizontal driver 220 as an internal circuit 302. The semiconductor chip 301 has output pads (not depicted) consecutively disposed on the side near the LCD panel for driving the data lines S1, S2, . . . S384 therein, input pads disposed on the side opposing the output pads for receiving the start pulse, shift direction switching signal, clock signal, input data, and latch control signal, and power source pads arranged adjacent to the input pads for receiving power sources and xcex3-correction sources. The output pads may be disposed at the shorter sides of the semiconductor chip 301.
Referring to FIG. 4, therein shown an example of the internal circuit 302, which is depicted to drive six data lines S1 to S6 out of 384 data lines as an abbreviation.
The internal circuit 302 includes a shift register 311, one stage of which corresponds to the number (six in this case) of data lines S1 to S6, a data register block 312 having registers in number (6) corresponding to the number of data lines S1 to S6, a first switch block 313 having three 2-input/2-output switches each for exchanging outputs from a pair of registers in the data register block 312, a latch block 314 having latch cells each for latching data output from the first switch block 313, a level shifter block 315 having level shifters each for level-shifting an output from the latch block 314, a D/A converter block 317 having three 2-input/2-output switches each for exchanging outputs from a pair of converter cells in the D/A converter block 316, and an output stage block 318 having voltage followers for transferring an output from the second switch block 317. These circuit elements in each circuit clock are consecutively arranged in the vicinity of the longer side of the semiconductor chip 301 near the LCD panel conforming to the arrangement of the data lines.
In operation of the internal circuit 302, if a right-shift operation, for example, is selected in the shift register 311, the shift register 311 reads a high level of the start pulse at a rising edge of the clock signal for each horizontal period, and delivers the start pulse toward the next stage disposed at the right hand side in the internal circuit 302. At the same time, the control signals for receiving data are also delivered to the registers in the data register block 312. The data register block 312 receives 6-bit display data by the registers therein based on the control signal supplied from the shift register 311 for each horizontal period. The display data receive in the i-th (odd-numbered) registers (i=,1 3, 5,) are delivered to the first input of the switches whereas the display data received in the (i+1)th (even-numbered) registers are delivered to the second input of the switches. The first switch block 313 alternately delivers the data received from the first inputs and the second inputs of the switches to the i-th and (i+1)th latches, respectively, in the latch blocks 314.
The latch block 314 delivers the latched display data at a time through the level shifter block 315 to the D/A converter block 316 at the rising edge of the latch control signal. The D/A converter block 316 receives the display data at the inputs of converter cells, i.e., N-ROM decoders 316N and P-ROM decoders 316P disposed therein. The D/A converter block 316 generates gray-scale level signals each having a negative polarity based on the display data received by the N-ROM decoders 316N, and delivers the gray-scale level signals to the first inputs of the switches in the second switch block 317. The D/A converter block 316 generates gray-scale level signals each having a positive polarity based on the display data received by the P-ROM decoders 316P, and delivers the gray-scale level signals to the second inputs of the switches in the second switch block 317.
The second switch block 317 delivers the gray-scale level signals to the voltage followers in the output stage block 318 so that gray-scale level signals having the negative polarity and the positive polarity are alternately delivered and that each i-th voltage follower for i=1, 3 and 5 and a corresponding (i+1)-th voltage follower receive gray-scale level signals having opposite polarities in a signal horizontal period. Thus, the voltage follower block 318 delivers the gray-scale level signals so that each odd-numbered data line and each even-numbered data line are driven by gray-scale level signals having opposite polarities and both the data lines are driven alternately by a gray-scale level signal having a positive polarity in a single horizontal period.
Referring to FIG. 5, the P-ROM decoder 316P in the D/A converter block 316 includes a plurality of enhancement pMOSFETs 1P and a plurality of depression pMOSFETs 2P arranged in a matrix with 64 rows (corresponding to gray-scale levels) and 12 columns (corresponding to six bits of the display data). The depression pMOSFET 2P is normally ON, whereas the enhancement pMOSFET 1P is normally OFF. Each enhancement pMOSFET 1P and a corresponding depression pMOSFET 2P connected in series form a pair for representing xe2x80x9c0xe2x80x9d or xe2x80x9c1xe2x80x9d of a bit. The order of the enhancement pMOSFET and the depression pMOSFET in each pair follows xe2x80x9c0xe2x80x9d or xe2x80x9c1xe2x80x9d of the bit.
Each row includes six pairs of pMOSFETs connected in series and corresponds to one of possible 6-bit gray-scale levels (000000) to (111111). The pMOSFETs in each column have gates connected together, which are applied with a bit DP1 to DP6 or inverted bit /DP1 to /DP6 of a display data. More specifically, the common gates of pMOSFETs in each odd-numbered row are applied with a corresponding one of the bits DP1 to DP6 of the display data, whereas the common gates of pMOSFETs in each even-numbered row are applied with a corresponding one of inverted bits /DP1 to /DP6 of the display data. The source of the pMOSFET in the first column in each row is applied with a gray-scale voltage VP1 . . . VP64 having a positive polarity. The drains of the pMOSFETs arranged in the last column are connected together to the output line of the P-ROM decoder and delivers one of gray-scale voltages VP1 to VP64 as a gray-scale level signal corresponding to the display data to the next stage.
Referring to FIG. 6, the N-ROM decoder 316N in the DIA converter block 316 includes a plurality of enhancement nMOSFETs 1N and a plurality of depression nMOSFETs 2N arranged in a matrix with 64 rows and 12 columns. The depression nMOSFET 2N is normally ON, whereas the enhancement nMOSFET IN is normally OFF. Each enhancement nMOSFET and a corresponding depression nMOSFET connected in series form a pair for representing xe2x80x9c0xe2x80x9d or xe2x80x9c1xe2x80x9d of a bit. The order of the enhancement nMOSFET 1N and the depression nMOSFET 2N in each pair follows xe2x80x9c0xe2x80x9d or xe2x80x9c1xe2x80x9d of the bit.
Each row includes six pairs of nMOSFETs connected in series and corresponds to one of possible 6-bit gray-scale levels (000000) to (111111). The nMOSFETs in each column have gates connected together, which are applied with a bit DN1 to DN6 or inverted bit /DN1 to /DN6 of a display data. More specifically, the common gates of nMOSFETs in each odd-numbered row are applied with a corresponding one of the bits DN1 to DN6 of the display data, whereas the common gates of nMOSFETs in each even-numbered row are applied with a corresponding one of inverted bits /DN1 to /DN of the display data. The drain of the nMOSFET in the first column in each row is applied with one of gray-scale voltages VN1 . . . VN64 having a negative polarity. The sources of the nMOSFETs arranged in the last column are connected together to the output line of the N-ROM decoder and delivers one of gray-scale voltages VN1 to VN64 as a gray-scale level signal corresponding to the display data to the next stage.
In operation of the decoders 316P and 316N, each row is applied with a corresponding one of gray-scale level voltages VP1 to VP64 or VN1 to VN64 at the first column. On the other hand, the gates of each pair of MOSFETs in the each row are applied with a corresponding bit of a display data and an inverted bit of the display data, respectively. If all the pMOSFETs in one of the rows are ON, the fray-scale level voltage applied to the row is delivered to the next stage block as a gray-scale level signal corresponding to the 6-bit display data.
Referring to FIG. 7 showing the arrangement of the decoders 316P and 316N, the P-ROM decoders 316P and the N-ROM decoders 316N are arranged alternately along the longer side of the semiconductor chip 301. Each P-ROM decoder 316P is disposed in an n-well 12 formed in a p-type semiconductor substrate 11, whereas each N-ROM decoder 316N is disposed in the p-type region of the semiconductor substrate 11.
Each MOSFET arranged in the first column of each decoder 316P or 316N is applied with a corresponding gray-scale voltage VP1, VN1, VP2, VN2 . . . , VP64 or VN64 at the source or drain (marked by a circular dot) thereof All the MOSFETs arranged in the last column in each decoder 316P or 316N are connected together at the drains or sources (each marked by a square dot) thereof to the output line VPO or VNO of each decoder. The output line delivers one of the gray-scale voltages VP1, VN1, . . . , VP64 and VN64 as a gray-scale signal corresponding to the 6-bit display data input thereto.
In the arrangement of the P-ROM decoders 316P and N-ROM decoders 316N as described above, there is a problem in that a relatively large space is necessary between the P-ROM decoder 316P and the adjacent N-ROM decoder 316N, thereby increasing the dimension along the longer side of the semiconductor chip.
In addition, since the signal lines 25P and 25N carrying a positive-polarity voltage and a negative-polarity voltage are mixed in each decoder area, the space between the signal lines 25P and 25N must be large, which increases the dimension along the shorter side of the semiconductor chip 301.
In view of the above, it is an object of the present invention to provide a drive unit for driving an LCD device in a dot reversible driving scheme, which has smaller dimensions compared to the conventional drive unit as described above.
The present invention provides an LCD driver in a drive unit for driving a plurality of data lines of an LCD panel, the LCD driver comprising a plurality of circuit blocks arranged in an internal circuit of a semiconductor chip, each of the circuit blocks having a data register block including a plurality of data registers each for receiving a display data for one of the data lines, a D/A converter block including a plurality of P-ROM decoders and a plurality of N-ROM decoders each disposed for a corresponding one of the data registers to output an analog gray-scale signal, and an output stage block each disposed for a corresponding one of the P-ROM decoders and the N-ROM decoders, the output stage block driver a corresponding one of the data lines based on an output from a corresponding one of the P-ROM decoders and the N-ROM decoders, and a switching system for switching the display data and the analog gray-scale signal so that adjacent two data lines receive the analog gray-scale signals having opposite polarities and also receive alternately the analog gray-scale signal having a positive polarity and the analog gray-scale signal having a negative polarity, the P-ROM decoders and the N-ROM decoders forming an N-ROM decoder block and a P-ROM decoder block, respectively, which are arranged consecutively along a side of the semiconductor chip.
In accordance with the present invention, although the locations of the P-ROM decoders and the N-ROM decoders do not match with the arrangement of the data lines, the switching system switches the display data and the analog gray-scale signals so that gray-scale signals decoded by the P-ROM decoders and the N-ROM decoders suitably drive the data lines. The arrangement of the P-ROM decodes in the P-ROM decoder block and the N-ROM decoders in the P-ROM decoder block affords reduction of the dimensions of the semiconductor chip.